x86: Enable TSC_RELIABLE for AMD servers

Except for a published BIOS errata on family 11h processors,
all AMD servers that have the Invariant TSC bit set have
a reliable TSC so Xen should not write to the TSC.

Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com>
Acked-by: Mark Langsdorf <mark.langsdorf@amd.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index d7d3fe7cd7362917b255aea98429d1fbbea684ba..94f35770e5bd986bd4e9fa77979edf6a02da0ed2 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -465,6 +465,8 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
                if (c->x86_power & (1<<8)) {
                        set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
                        set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+                       if (c->x86 != 0x11)
+                               set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
                }
        }